DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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15.3.16. Parallel Pipelined FFT (PFFT_Pipe)

The PFFT_Pipe block implements a supersampled FFT (or IFFT) that processes 2M points per cycle (with 0 < M).

The PFFT_Pipe block uses a pipeline of (small) fully-parallel FFTs, twiddle, and transpose blocks. This FFT uses only a small number of DSP blocks but has a relative high latency (and associated memory usage).

Not all parameters are available with all blocks.

Table 131.  Parameters for the PFFT_Pipe Blocks
Parameter Description
iFFT true to implement an IFFT otherwise false.
N Log2 of the number of points in the FFT.
Bit-reversed input true if you expect bit-reversed input, otherwise false. .
Number of spatial bits M for 2M wires.
Twiddle/pruning specification( -.
Use faithful rounding true if the block uses faithful (rather than correct) rounding for floating-point operations. Fixed-point FFTs ignore this parameter.
Table 132.  Port Interface for the PFFT_Pipe Blocks
Signal Direction Type Description
v Input Boolean. Valid input signal.
d Input Any. Complex data input signal.
qv Output Boolean. Valid output signal.
q Output Determined by pruning specification. Complex data output signal.