DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.13.17. Dynamic Decimating FIR Filter

The dynamic decimating FIR reference design offers multichannel run-time decimation ratios in integer power of 2 and run-time control of channel count (in trading with bandwidth).The design supports dynamic channel count to signal bandwidth trade off (if you halve the channel count, the input sample rate doubles).

The FIR filter length is 2 x (Dmax / Dmin) x N + 1 where Dmax and Dmin are the maximum and minimum decimation ratios and N is the number of (1 sided) symmetric coefficients at Dmin.

All channels must have the same decimation ratio. The product of the number of channels and the minimum decimation ratio must be 4 or more. The design limits the wire count to 1 and:

number of channels x sample rate = clock rate.

The model file is demo_dyndeci.mdl