DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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15.4.33. Loadable Counter (LoadableCounter)

The LoadableCounter block maintains a counter that you can reload with new parameters as needed in-circuit. The value of the counter increments by the step value every cycle for which the enable input is high. If the counter exceeds or equals the modulo value, or underflows in the case of a negative step value, it wraps around to zero or the value minus the modulo value as applicable. The current counter value is always available from the block's only output.

Internal registers hold the value, modulo, and step size of the counter. The values of these registers on reset are parameters that you can set on the block. Additionally, you can reload these registers with new values in-circuit by raising the ld signal high. While ld is high, DSP Builder writes the values of the i, s, and m input signals into the value, step, and modulo registers, respectively. The value of i passes through to the counter output. When ld falls low again, the counter resumes its normal operation starting from these new values.

If the initial or step values exceed the modulo value, the behavior is undefined. Using signed step values increases logic usage in hardware.

Table 207.  Parameters
Parameter Description
Counter setup A vector that specifies the counter settings on reset in the following format:

[<initial value> <modulo> <step size>]

Table 208.  Signals
Signal Direction Type Description Vector Data Support Complex Data Support
en Input Boolean Enable the counter. Yes No
ld Input Boolean Load the counter. Yes No
i Input Any unsigned integer New initial value to load. Yes No
s Input Any integer New step value to load. Yes No
m Input Any non-zero unsigned integer New modulo value to load. Yes No
q Output Unsigned integer Counter value. Yes No