DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.14.2. Four Channel, Two Banks NCO

This design example implements an NCO with four channels and two banks.

This design example demonstrates frequency-hopping with the NCO block to generate four channels of sinusoidal waves that you can switch from one set (bank) of frequencies to another.

The phase increment values are set directly into the NCO Parameter dialog box as a 2 (rows) × 4 (columns) matrix. The input for the bank index is set up so that it alternates between the two predefined banks with each one lasting 2000 steps.

A BusStimulus block sets up an Avalon-MM interface that writes into the phase increment memory registers. It shows how you can use the Avalon-MM interface to dynamically change the frequencies of the NCO-generated sinusoidal signals at run time. This design example uses a 16-bit memory interface (as the Control block specifies) and a 24-bit the accumulator in the NCO block. The design example requires two registers for each phase increment value. With the base address of the phase increment memory map set to 1000 in this design example, the addresses [1000 1001 1002 1003 1012 1013 1014 1015] write to the phase increment memory registers of channels 1 and 2 in bank 1, and to the registers of channels 3 and 4 in bank 2. The write data is also made up of two parts with each part writing to one of the registers feeding the selected phase increment accumulators.

This design example has two banks of frequencies with each bank processes 2,000 steps before switching to the other. You should write a new value into the phase increment memory register for each bank to change the NCO output frequencies after 8,000 steps during simulation. To avoid writing new values to the active bank, the design example configures the write enable signals in the following way:

[zeros(1,7000) 1 1 1 1 zeros(1,2000) 1 1 1 1 zeros(1,8000)]

This configuration ensures that a new phase increment value for bank 0 is written at 7000 steps when the NCO is processing bank 1; and a new phase increment value for bank 1 is written at 9000 steps when the NCO is processing bank 0.

Four writes for each bank exist to write new values for channel 1 and 2 into bank 0, and new values for channel 3 and 4 into bank 1. Each new phase value needs two registers due to the size of the memory interface.

The Spectrum Scope block shows three peaks for a selected channel with the first two peaks representing the two banks and the third peak showing the frequency that you specify through the memory interface. The scope of the select channel shows the sinusoidal waves of the channel you select. You can zoom in to see the smooth and continuous sinusoidal signals at the switching point. You can also see the frequency changes after 8000 steps where the phase increment value alters through the memory interface.

The top-level testbench includes Control, Signals, BusStimulus, Run ModelSim, and Run Quartus Prime blocks, plus ChanView blocks that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_mc_nco_2banks_mem_interface.m script.

The NCOSubSystem subsystem includes the Device and NCO blocks.

The model file is demo_mc_nco_2banks_mem_interface.mdl.

Note: This design example uses the Simulink Signal Processing Blockset.

Did you find the information on this page useful?

Characters remaining:

Feedback Message