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- 15.3.12. Fully-Parallel FFTs with Flexible Ordering (FFT2X, FFT4X, FFT8X, FFT16X, FFT32X, and FFT64X)
- 15.3.13. General Multitwiddle and General Twiddle (GeneralMultiTwiddle, GeneralMultVTwiddle, GeneralTwiddle, GeneralVTwiddle)
9.6.5. Latency and fMAX Constraint Conflicts in DSP Builder Designs
Generally, problems occur in feedback loops. You can solve these issues by lowering the fMAX target, or by restructuring the feedback loop to reduce the combinatorial logic or increasing the delay. You can redesign some control structures that have feedback loops to make them completely feed forward.
You cannot set a latency constraint that conflicts with the constraint that the fMAX target implies. For example, a latency constraint of < 2 may conflict with the fMAX implied pipelining constraint. The multiplier may need four pipelining stages to reach the target fMAX. The simulation fails and issues an error, highlighting the Primitive subsystem.
DSP Builder gives this error because you must increase the constraint limit by at least 3 (that is, to < 5) to meet the target fMAX.
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