DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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6.5. Doubling the Target Clock Rate for a DSP Builder IP Design

Create an IP design.


  1. Double-click the EditParams block to open my_firi.m in the MATLAB Editor. Change my_firi_param.ClockRate to 480.0 and click Save.
  2. Simulate the design.
  3. Click DSP Builder > Verify Design, and click Clear Results to clear the output pane.
  4. Click Run Verification.