DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.13.5. 4-Carrier, 2-Antenna W-CDMA DDC

This reference design uses IP and Interface blocks to build a 16-channel, 2-antenna, multiple-frequency modulation DDC for use in an IF modem design compatible with the W-CDMA standard.

The top-level testbench includes Control, Signals, and Run Quartus Prime blocks, plus a ChanView block that isolates two channels of data from the TDM signals.

The DDCChip subsystem includes Device, DecimatingCIC, Decimating FIR, Mixer, NCO, and Scale blocks. It also contains a Sync subsystem which provides the synchronization of the channel data to the NCO carrier waves.

The CIC and FIR filters implement a decimating filter chain that down converts the eight complex carriers (16 real channels from two antennas with four pairs of I and Q inputs from each antenna) from a frequency of 122.88 MSPS to a frequency of 7.68 MSPS (a total decimation rate of 16). The real mixer and NCO isolate the four channels. The design configures the NCO with four channels to provide four pairs of sine and cosine waves at frequencies of 12.5 MHz, 17.5 MHz, 22.5 MHz, and 27.5 MHz, respectively. The NCO has the same sample rate (122.88 MSPS) as the input data sample rate.

The Sync subsystem shows how to manage two data streams that come together and synchronize. The data from the NCOs writes to a memory with the channel as an address. The data stream uses its channel signals to read out the NCO signals, which resynchronizes the data correctly.

A system clock rate of 245.76 MHz drives the design on the FPGA, which the Device block defines inside the DDCChip subsystem.

The model file is wcdma_multichannel_ddc_mixer.mdl.

Note: This reference design uses the Simulink Signal Processing Blockset.