DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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Document Table of Contents Scheduled Synthesis

The Scheduled style of operation uses a pipelining and delay distribution algorithm that creates fast hardware implementations from an easily described untimed block diagram. This style takes full advantage of the automatic pipelining capability.

The algorithm performs the following operations:

  1. Reads in and flattens your design example for any subsystem that contains a SynthesisInfo block.
  2. Builds an internal graph to represent the logic.
  3. Based on the absolute clock frequency requested, adds enough pipeline stages to meet that clock frequency. For example, you may pipeline long adders into several shorter adders. This additional pipelining helps reach high clock frequencies.