DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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7.12.8. Fibonacci Series

This DSP Builder design example generates a Fibonacci sequence.

This design example shows that even for circuitry with tight feedback loops and 120-bit adders, designs can achieve high data rates by the pipelining algorithms. The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks. The Chip subsystem includes the Device block and a lower level FibSystem subsystem. The FibSystem subsystem includes ChannelIn, ChannelOut, SampleDelay, Add, Mux, and SynthesisInfo blocks.

Note: In this design example, the top-level of the FPGA device (marked by the Device block) and the synthesizable Primitive subsystem (marked by the SynthesisInfo block) are at different hierarchy levels.

The model file is demo_fibonacci.mdl.