DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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15.6.3. Enabled Delay Line

The DSP Builder Enabled Delay Line block takes a single data signal a and an enable signal e and implements an enabled delay line, with q as the delayed data output. Internally, the block is is either a Latch_0L or Latch_1L (depending on the Zero or one initial delay parameter) followed by a series of Latch_1Ls. The final output connects to the output port q. When you use the block in a feedback loop, DSP Builder cannot redistribute the enabled sample delays around the feedback path. In these instances, use the Enabled Feedback Delay block."