DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.13.9. 1-Carrier, 2-Antenna W-CDMA DDC

This reference design uses IP and Interface blocks to build a 4-channel, 2-antenna, single-frequency modulation DUC for an IF modem design compatible with the W-CDMA standard.

The top-level testbench includes Control, Signals, and Run Quartus Prime blocks. A Spectrum Scope block computes and displays the periodogram of the outputs from the two antennas.

The DUCChip subsystem includes a Device block to specify the target FPGA device, and a DUC subsystem that contains InterpolatingFIR, InterpolatingCIC, NCO, ComplexMixer, and Scale blocks.

The FIR and CIC filters implement an interpolating filter chain that up convert the four channel input data from a frequency of 3.84 MSPS to a frequency of 122.88 MSPS (a total interpolation factor of 32). The complex mixer and NCO modulate the four channel baseband input signal onto the IF region.

The design example configures the NCO with a single channel to provide one sine and one cosine wave at a frequency of 17.5 MHz. The NCO has the same sample rate (122.88 MSPS) as the final interpolated output sample rate from the last CIC filter in the interpolating filter chain.

A system clock rate of 122.88 MHz drives the design on the FPGA, which the Device block defines inside the DDC subsystem.

The model file is wcdma_picocell_duc_mixer.mdl.

Note: This reference design uses the Simulink Signal Processing Blockset.