DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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15.3.3. Butterfly Unit (BFU)

The BFU, BFU_long BFU_short, and BFU_simple blocks each implement a butterfly unit for use in floating-point streaming FFTs.

The BFU_long block corresponds to a classical radix-22 butterfly I block plus its associated feedback path.

The BFU_short block has exactly the same functionality, but it uses only one floating-point adders. It uses twice as many memory resources as the BFU_long block, but also uses considerably less logic resources.

The BFU block automatically reconfigures to use either BFU_long or BFU_short to minimize the total (memory plus logic) resource usage.

Each BFU block performs a two-point FFT pass over a block of data of size 2N (where N is a compile-time parameter).

During the first 2(N–1) cycles, the control signal, s, is 0. During this time, the BFU block stores the first half of the input block.

During the second 2(N–1) cycles, s is 1. During this time, the BFU block reads the second half of the input block and produces the first result of each of 2(N–1) two-point FFTs on the output.

During the third 2(N–1) cycles, s is 0 again. During this time, the BFU unit produces the second result of each of the 2(N–1) two-point FFTs, while simultaneously storing the first half of the next input block.

Table 102.  Parameters for the BFU Block
Parameter Description
N Specifies the input block size to be 2N.
Table 103.  Port Interface for the BFU Block
Signal Direction Type Description
d Input Any floating-point type. Input samples.
q Output Same as d. Output results.
s Input Boolean. Control pin. Drive with external logic. Ensure it is 0 for 2(N-1) cycles and 1 for the next 2(N-1) cycles.