DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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Document Table of Contents

10.1.4. Using ALU Folding

Note: In the ChannelIn and ChannelOut blocks, before you use ALU folding, ensure you turn off Folding enabled.


  1. Open the top-level design that contains the primitive subsystem you want to add ALU folding to.
  2. Save a backup of your original design.
  3. Replace:
    • Constant multiplier blocks with multipliers blocks.
    • Reciprocal blocks with Divide blocks
    • Sin(πx) blocks with sin(x) blocks.
  4. Avoid low-level bit manipulation
  5. Open the primitive subsystem (which contains the ChannelIn and ChannelOut blocks) and add an ALU Folding block from the DSP Builder Utilities library.
  6. Double click the ALU Folding block to open the Block Parameters window.
  7. Enter a value for Sample rate (MHz).
  8. Enter a value for Maximum latency (cycles)
  9. Turn off Register Outputs to make the output format the same as the input format. Turn on Register Outputs, so that the outputs hold their values until the next data sample output occurs.
  10. Select the Simulation rate
  11. Simulate your design.
    DSP Builder generates HDL for the folded implementation of the subsystem and a testbench. The testbench verifies the sample rate Simulink simulation against a clock rate ModelSim simulation of the generated HDL.