DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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7.12.27. Vector Initialization of Sample Delay

This DSP Builder design example shows that one sample delay can replace what usually requires a Demultiplex, SampleDelay, and Multiplex combination.

When the SampleDelay Primitive library block receives vector input, you can independently specify a different delay for each of the components of the vector.

You may give individual components zero delay resulting in a direct feed through of only that component. Avoid algebraic loops if you select some components to be zero delays.

This rule only applies when DSP Builder is reading and outputting vector data. A scalar specification of delay length still sets all the delays on each vector component to the same value. You must not specify a vector that is not the same length as the vector on the input port. A negative delay on any one component is also an error. However, as in the scalar case, you can specify a zero length delay for one or more of the components.

The model file is demo_sample_delay_vector.mdl.