DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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16.1.1. Capture Values

The Capture Values block can capture a variable number of signal inputs and supports vector and complex types.

You can add the block anywhere in the Simulink design. The block only supports the .vcd file format. DSP Builder writes this file in the RTL directory and it derives its name from the name given to the block. The specific arrangement of .vcd is based on what ModelSim writes out - i.e. only Boolean wires are used. You can import it into ModelSim using the vcd2wlf tool. The waveforms should match with those generated by the HDL simulation, although you might see an offset because of the Simulink model latency correction.