Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Public
Document Table of Contents

4.3.2.3. Resetting the Receiver During Device Operation

The numbers in this list correspond to the numbers in the following figure.

  1. Assert rx_analogreset and rx_digitalreset while rx_cal_busy is low.
  2. Wait for rx_analogreset_ack to go high, to ensure successful assertion of rx_analogreset. rx_analogreset_ack goes high when TRS has successfully completed the reset request for assertion.
    1. Deassert rx_analogreset.
  3. Wait for rx_analogreset_ack to go low, to ensure successful deassertion of rx_analogreset. rx_analogreset_ack goes low when TRS has successfully completed the reset request for deassertion.
  4. The rx_is_lockedtodata signal goes high after the CDR acquires lock.
  5. Ensure rx_is_lockedtodata is asserted for tLTD (minimum of 4 μs) before deasserting rx_digitalreset.
Figure 158. Receiver Reset Sequence During Device Operation