Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Public
Document Table of Contents

2.11. Implementing Protocols in Intel® Cyclone® 10 GX Transceivers Revision History

Document Version Changes
2019.12.13 Made the following changes to the "1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core" section:
  • Updated the Clocking and Reset Sequence topic to state that the 1G/ 2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP core for Intel® Cyclone® 10 GX devices supports up to ±100 ppm clock frequency difference for a maximum packet length of 16,000 bytes.
2019.06.12 Made the following change:
  • Clarified that the Enhanced PCS only supports the static polarity inversion feature, but the Standard PCS supports both the static and dynamic polarity inversion features.
2019.05.13 Made the following change:
  • Renamed Altera Debug Master Endpoint (ADME) to Native PHY DebugMaster Endpoint (NPDME).
  • Updated Table: Ethernet Acronyms.
2018.09.24 Made the following changes to the "Using the Cyclone 10 GX Transceiver Native PHY IP Core" section:
  • Added details about how to enable the transceiver toolkit capability in the "Dynamic Reconfiguration Parameters" section.
Made the following changes to the "1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core" section:
  • Added this section.
2017.12.04 Made the following changes:
  • Removed the tx_pma_txdetectrx[<n>-1:0] port from the "TX PMA Ports" table.
2017.11.30
Made the following changes in the "PCI Express" section:
  • Removed the following parameters from the "Parameters for Intel® Cyclone® 10 GX Native PHY IP in PIPE Gen1, Gen2 Modes - TX PMA" table:
    • Enable tx_pma_qpipullup port (QPI)
    • Enable tx_pma_qpipulldn port (QPI)
    • Enable tx_pma_txdetectrx port (QPI)
    • Enable tx_pma_rxfound port (QPI)
  • Removed the Enable rx_pma_qpipulldn port (QPI) parameter from the "Parameters for Intel® Cyclone® 10 GX Native PHY IP in PIPE Gen1, Gen2 Modes - RX PMA" table.
Made the following changes to the "Using the Transceiver Native PHY IP Core" section:
  • Removed the QPI protocol mode from the PMA configuration rules parameter in the "General, Common PMA Options, and Datapath Options" table.
  • Removed the following parameters from the "TX PMA Parameters" table:
    • Enable tx_pma_qpipullup port (QPI)
    • Enable tx_pma_qpipulldn port (QPI)
    • Enable tx_pma_txdetectrx port (QPI)
    • Enable tx_pma_rxfound port (QPI)
2017.11.06
Made the following changes to the "Other Protocols" section:
  • Changed Native PHY IP data rate to 12.5 from 10.3125
Made the following changes to the "PCI Express" section:
  • Added note "Connect pll_pcie_clk from either ATX PLL or fPLL to the pipe_hclk_in port on Native PHY" in figure "Use fPLL for Gen1/Gen2 x1 Mode".
  • Changed the clock frequency differential in the "Gen1 and Gen2 Clock Compensation" section introduction paragraph.
Made the following changes to the "Transceiver Design Flow Overview" section:
  • Added a note "Link training, auto speed negotiation and sequencer functions are not included in the Native PHY IP. The user would have to create soft logic to implement these functions when using Native PHY IP" in the "Transceiver Protocols and PHY IP Support" section.
  • Added a row for "CPRI 4.1/OBSAI RP3 v4.1" protocol in the "Transceiver Protocols and PHY IP Support" section.
  • Added footnote "For x2 and x4 modes, select PCIe PIPE Gen2 x8. Then change the number of data channels from 8 to 4. " for "PCIe Gen2 x1, x2, x4" protocol in the "Transceiver Protocols and PHY IP Support" section.
  • Added footnotes in the "Transceiver Protocols and PHY IP Support" section.
  • Updated protocol presets for "SD-SDI/HD-SDI/3G/6G/12G-SDI ", "DisplayPort" and "CPRI 4.1/OBSAI RP3 v4.1" protocols in the "Transceiver Protocols and PHY IP Support" section.
  • Added a note that Intel® Cyclone® 10 GX is only supported with Intel® Quartus® Prime Pro Edition 17.1 and future versions in the "Transceiver Design IP Blocks" section.
  • Added a note " Intel® Cyclone® 10 GX only supported with Intel® Quartus® Prime Pro Edition 17.1 and future versions."
  • Added a note "Link training, auto speed negotiation and sequencer functions are not included in the Native PHY IP. The user would have to create soft logic to implement these functions when using Native PHY IP. " in the "Protocols and PHY IP Support" table.
  • Added CPRI 4.1/OBSAI RP3 v4.1 protocol in "Protocols and PHY IP Support" table.
Made the following changes in the "10GBASE-R" section:
  • Added the "Native PHY IP Parameter Settings for 10GBASE-R and 10GBASE-R with IEEE 1588v2" section.
  • Changed the range of values for the Number of data channels parameter in the "General and Datapath Parameters" table.
  • Changed the range of values for the Initial TX PLL clock input selection parameter in the "TX PMA Parameters" table.
Made the following changes to the "Gigabit Ethernet (GbE) and GbE with 1588" section:
  • Changed the note in the "Rate Match FIFO for GbE" section.
  • Added the "Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2" section.
Made the following changes to the "Using the Intel® Cyclone® 10 GX Transceiver Native PHY IP Core" section:
  • Added this chapter.
2017.05.08 Initial release.