1. Intel® Cyclone® 10 GX Transceiver PHY Overview
2. Implementing Protocols in Intel® Cyclone® 10 GX Transceivers
3. PLLs and Clock Networks
4. Resetting Transceiver Channels
5. Cyclone® 10 GX Transceiver PHY Architecture
6. Reconfiguration Interface and Dynamic Reconfiguration
7. Calibration
8. Analog Parameter Settings
2.1. Transceiver Design IP Blocks
2.2. Transceiver Design Flow
2.3. Cyclone® 10 GX Transceiver Protocols and PHY IP Support
2.4. Using the Cyclone® 10 GX Transceiver Native PHY IP Core
2.5. Interlaken
2.6. Ethernet
2.7. PCI Express (PIPE)
2.8. CPRI
2.9. Other Protocols
2.10. Simulating the Transceiver Native PHY IP Core
2.11. Implementing Protocols in Intel® Cyclone® 10 GX Transceivers Revision History
2.2.1. Select and Instantiate the PHY IP Core
2.2.2. Configure the PHY IP Core
2.2.3. Generate the PHY IP Core
2.2.4. Select the PLL IP Core
2.2.5. Configure the PLL IP Core
2.2.6. Generate the PLL IP Core
2.2.7. Reset Controller
2.2.8. Create Reconfiguration Logic
2.2.9. Connect the PHY IP to the PLL IP Core and Reset Controller
2.2.10. Connect Datapath
2.2.11. Make Analog Parameter Settings
2.2.12. Compile the Design
2.2.13. Verify Design Functionality
2.4.1. Presets
2.4.2. General and Datapath Parameters
2.4.3. PMA Parameters
2.4.4. Enhanced PCS Parameters
2.4.5. Standard PCS Parameters
2.4.6. PCS Direct
2.4.7. Dynamic Reconfiguration Parameters
2.4.8. PMA Ports
2.4.9. Enhanced PCS Ports
2.4.10. Standard PCS Ports
2.4.11. IP Core File Locations
2.4.12. Unused Transceiver Channels
2.6.1.1. 8B/10B Encoding for GbE, GbE with IEEE 1588v2
2.6.1.2. Word Alignment for GbE, GbE with IEEE 1588v2
2.6.1.3. 8B/10B Decoding for GbE, GbE with IEEE 1588v2
2.6.1.4. Rate Match FIFO for GbE
2.6.1.5. How to Implement GbE, GbE with IEEE 1588v2 in Intel® Cyclone® 10 GX Transceivers
2.6.1.6. Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2
2.6.2.1. The XGMII Clocking Scheme in 10GBASE-R
2.6.2.2. How to Implement 10GBASE-R and 10GBASE-R with IEEE 1588v2 in Intel® Cyclone® 10 GX Transceivers
2.6.2.3. Native PHY IP Parameter Settings for 10GBASE-R and 10GBASE-R with IEEE 1588v2
2.6.2.4. Native PHY IP Ports for 10GBASE-R and 10GBASE-R with IEEE 1588v2 Transceiver Configurations
2.7.1. Transceiver Channel Datapath for PIPE
2.7.2. Supported PIPE Features
2.7.3. How to Connect TX PLLs for PIPE Gen1 and Gen2 Modes
2.7.4. How to Implement PCI Express (PIPE) in Cyclone® 10 GX Transceivers
2.7.5. Native PHY IP Parameter Settings for PIPE
2.7.6. fPLL IP Parameter Core Settings for PIPE
2.7.7. ATX PLL IP Parameter Core Settings for PIPE
2.7.8. Native PHY IP Ports for PIPE
2.7.9. fPLL Ports for PIPE
2.7.10. ATX PLL Ports for PIPE
2.7.11. How to Place Channels for PIPE Configurations
2.7.2.1.1. Dynamic Switching Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps)
2.7.2.1.2. Transmitter Electrical Idle Generation
2.7.2.1.3. Power State Management
2.7.2.1.4. 8B/10B Encoder Usage for Compliance Pattern Transmission Support
2.7.2.1.5. Receiver Status
2.7.2.1.6. Receiver Detection
2.7.2.1.7. Gen1 and Gen2 Clock Compensation
2.7.2.1.8. PCIe Reverse Parallel Loopback
2.9.1.1. How to Implement the Basic (Enhanced PCS) Transceiver Configuration Rules in Cyclone® 10 GX Transceivers
2.9.1.2. Native PHY IP Parameter Settings for Basic (Enhanced PCS)
2.9.1.3. How to Enable Low Latency in Basic Enhanced PCS
2.9.1.4. Enhanced PCS FIFO Operation
2.9.1.5. TX Data Bitslip
2.9.1.6. TX Data Polarity Inversion
2.9.1.7. RX Data Bitslip
2.9.1.8. RX Data Polarity Inversion
2.9.2.1. Word Aligner Manual Mode
2.9.2.2. Word Aligner Synchronous State Machine Mode
2.9.2.3. RX Bit Slip
2.9.2.4. RX Polarity Inversion
2.9.2.5. RX Bit Reversal
2.9.2.6. RX Byte Reversal
2.9.2.7. Rate Match FIFO in Basic (Single Width) Mode
2.9.2.8. Rate Match FIFO Basic (Double Width) Mode
2.9.2.9. 8B/10B Encoder and Decoder
2.9.2.10. 8B/10B TX Disparity Control
2.9.2.11. How to Enable Low Latency in Basic
2.9.2.12. TX Bit Slip
2.9.2.13. TX Polarity Inversion
2.9.2.14. TX Bit Reversal
2.9.2.15. TX Byte Reversal
2.9.2.16. How to Implement the Basic, Basic with Rate Match Transceiver Configuration Rules in Cyclone® 10 GX Transceivers
2.9.2.17. Native PHY IP Parameter Settings for Basic, Basic with Rate Match Configurations
3.1. PLLs
3.2. Input Reference Clock Sources
3.3. Transmitter Clock Network
3.4. Clock Generation Block
3.5. FPGA Fabric-Transceiver Interface Clocking
3.6. Transmitter Data Path Interface Clocking
3.7. Receiver Data Path Interface Clocking
3.8. Unused/Idle Clock Line Requirements
3.9. Channel Bonding
3.10. PLL Feedback and Cascading Clock Network
3.11. Using PLLs and Clock Networks
3.12. PLLs and Clock Networks Revision History
4.1. When Is Reset Required?
4.2. Transceiver PHY Implementation
4.3. How Do I Reset?
4.4. Using the Transceiver PHY Reset Controller
4.5. Using a User-Coded Reset Controller
4.6. Combining Status or PLL Lock Signals
4.7. Timing Constraints for Bonded PCS and PMA Channels
4.8. Resetting Transceiver Channels Revision History
4.3.2.1. Recommended Reset Sequence
4.3.2.2. Resetting the Transmitter During Device Operation
4.3.2.3. Resetting the Receiver During Device Operation
4.3.2.4. Dynamic Reconfiguration of Transmitter Channel Using the Acknowledgment Model
4.3.2.5. Dynamic Reconfiguration of Receiver Channel Using the Acknowledgment Model
5.2.1.1. Enhanced PCS TX FIFO
5.2.1.2. Interlaken Frame Generator
5.2.1.3. Interlaken CRC-32 Generator
5.2.1.4. 64B/66B Encoder and Transmitter State Machine (TX SM)
5.2.1.5. Pattern Generators
5.2.1.6. Scrambler
5.2.1.7. Interlaken Disparity Generator
5.2.1.8. TX Gearbox, TX Bitslip and Polarity Inversion
5.2.2.1. RX Gearbox, RX Bitslip, and Polarity Inversion
5.2.2.2. Block Synchronizer
5.2.2.3. Interlaken Disparity Checker
5.2.2.4. Descrambler
5.2.2.5. Interlaken Frame Synchronizer
5.2.2.6. 64B/66B Decoder and Receiver State Machine (RX SM)
5.2.2.7. Pseudo Random Pattern Verifier
5.2.2.8. 10GBASE-R Bit-Error Rate (BER) Checker
5.2.2.9. Interlaken CRC-32 Checker
5.2.2.10. Enhanced PCS RX FIFO
5.3.1.3.1. 8B/10B Encoder Control Code Encoding
5.3.1.3.2. 8B/10B Encoder Reset Condition
5.3.1.3.3. 8B/10B Encoder Idle Character Replacement Feature
5.3.1.3.4. 8B/10B Encoder Current Running Disparity Control Feature
5.3.1.3.5. 8B/10B Encoder Bit Reversal Feature
5.3.1.3.6. 8B/10B Encoder Byte Reversal Feature
5.3.2.1.1. Word Aligner Bit Slip Mode
5.3.2.1.2. Word Aligner Manual Mode
5.3.2.1.3. Word Aligner Synchronous State Machine Mode
5.3.2.1.4. Word Aligner Deterministic Latency Mode
5.3.2.1.5. Word Aligner Pattern Length for Various Word Aligner Modes
5.3.2.1.6. Word Aligner RX Bit Reversal Feature
5.3.2.1.7. Word Aligner RX Byte Reversal Feature
6.1. Reconfiguring Channel and PLL Blocks
6.2. Interacting with the Reconfiguration Interface
6.3. Configuration Files
6.4. Multiple Reconfiguration Profiles
6.5. Embedded Reconfiguration Streamer
6.6. Arbitration
6.7. Recommendations for Dynamic Reconfiguration
6.8. Steps to Perform Dynamic Reconfiguration
6.9. Direct Reconfiguration Flow
6.10. Native PHY IP or PLL IP Core Guided Reconfiguration Flow
6.11. Reconfiguration Flow for Special Cases
6.12. Changing PMA Analog Parameters
6.13. Ports and Parameters
6.14. Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks
6.15. Embedded Debug Features
6.16. Using Data Pattern Generators and Checkers
6.17. Timing Closure Recommendations
6.18. Unsupported Features
6.19. Cyclone® 10 GX Transceiver Register Map
6.20. Reconfiguration Interface and Dynamic Reconfiguration Revision History
8.1. Making Analog Parameter Settings using the Assignment Editor
8.2. Updating Quartus Settings File with the Known Assignment
8.3. Analog Parameter Settings List
8.4. Receiver General Analog Settings
8.5. Receiver Analog Equalization Settings
8.6. Transmitter General Analog Settings
8.7. Transmitter Pre-Emphasis Analog Settings
8.8. Transmitter VOD Settings
8.9. Dedicated Reference Clock Settings
8.10. Unused Transceiver Channels Settings
8.11. Analog Parameter Settings Revision History
8.7.1. XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_1T
8.7.2. XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_2T
8.7.3. XCVR_C10_TX_PRE_EMP_SIGN_1ST_POST_TAP
8.7.4. XCVR_C10_TX_PRE_EMP_SIGN_2ND_POST_TAP
8.7.5. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
8.7.6. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
8.7.7. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
8.7.8. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
2.4.7. Dynamic Reconfiguration Parameters
Dynamic reconfiguration allows you to change the behavior of the transceiver channels and PLLs without powering down the device. Each transceiver channel and PLL includes an Avalon® -MM slave interface for reconfiguration. This interface provides direct access to the programmable address space of each channel and PLL. Because each channel and PLL includes a dedicated Avalon® -MM slave interface, you can dynamically modify channels either concurrently or sequentially. If your system does not require concurrent reconfiguration, you can parameterize the Transceiver Native PHY IP to share a single reconfiguration interface.
You can use dynamic reconfiguration to change many functions and features of the transceiver channels and PLLs. For example, you can change the reference clock input to the TX PLL. You can also change between the Standard and Enhanced datapaths.
To enable Intel® Cyclone® 10 GX transceiver toolkit capability in the Native PHY IP core, you must enable the following options:
- Enable dynamic reconfiguration
- Enable Native PHY Debug Master Endpoint
- Enable capability registers
- Enable control and status registers
- Enable PRBS (Pseudo Random Binary Sequence) soft accumulators
Parameter | Value | Description |
---|---|---|
Enable dynamic reconfiguration | On/Off | When you turn on this option, the dynamic reconfiguration interface is enabled. |
Share reconfiguration interface | On/Off | When you turn on this option, the Transceiver Native PHY IP presents a single Avalon® -MM slave interface for dynamic reconfiguration for all channels. In this configuration, the upper [n-1:10] address bits of the reconfiguration address bus specify the channel. The channel numbers are binary encoded. Address bits [9:0] provide the register offset address within the reconfiguration space for a channel. |
Enable Native PHY Debug Master Endpoint | On/Off | When you turn on this option, the Transceiver Native PHY IP includes an embedded Native PHY Debug Master Endpoint (NPDME) that connects internally to the Avalon® -MM slave interface for dynamic reconfiguration. The NPDME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console. This option requires you to enable the Share reconfiguration interface option for configurations using more than one channel. |
Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE | On/Off | When enabled, the reconfig_waitrequest does not indicate the status of AVMM arbitration with PreSICE. The AVMM arbitration status is reflected in a soft status register bit. This feature requires that the "Enable control and status registers" feature under "Optional Reconfiguration Logic" be enabled. |
Parameter | Value | Description |
---|---|---|
Enable capability registers | On/Off | Enables capability registers that provide high level information about the configuration of the transceiver channel. |
Set user-defined IP identifier | User-defined | Sets a user-defined numeric identifier that can be read from the user_identifier offset when the capability registers are enabled. |
Enable control and status registers | On/Off | Enables soft registers to read status signals and write control signals on the PHY interface through the embedded debug. |
Enable PRBS (Pseudo Random Binary Sequence) soft accumulators | On/Off | Enables soft logic for performing PRBS bit and error accumulation when the hard PRBS generator and checker are used. |
Parameter | Value | Description |
---|---|---|
Configuration file prefix | <prefix> | Here, the file prefix to use for generated configuration files is specified. Each variant of the Transceiver Native PHY IP should use a unique prefix for configuration files. |
Generate SystemVerilog package file | On/Off | When you turn on this option, the Transceiver Native PHY IP generates a SystemVerilog package file, reconfig_parameters.sv. This file contains parameters defined with the attribute values required for reconfiguration. |
Generate C header file | On/Off | When you turn on this option, the Transceiver Native PHY IP generates a C header file, reconfig_parameters.h. This file contains macros defined with the attribute values required for reconfiguration. |
Generate MIF (Memory Initialization File) | On/Off | When you turn on this option, the Transceiver Native PHY IP generates a MIF, reconfig_parameters.mif. This file contains the attribute values required for reconfiguration in a data format. |
Include PMA analog settings in configuration files | On/Off | When enabled, the IP allows you to configure the PMA analog settings that are selected in the Analog PMA settings (Optional) tab. These settings are included in your generated configuration files.
Note: You must still specify the analog settings for your current configuration using Quartus Prime Setting File (.qsf) assignments in Quartus. This option does not remove the requirement to specify Quartus Prime Setting File (.qsf) assignments for your analog settings. Refer to the Analog Parameter Settings chapter in the Cyclone® 10 GX Transceiver PHY User Guide for details on using the QSF assignments.
|
Parameter | Value | Description |
---|---|---|
Enable multiple reconfiguration profiles | On/Off | When enabled, you can use the GUI to store multiple configurations. This information is used by Quartus to include the necessary timing arcs for all configurations during timing driven compilation. The Native PHY generates reconfiguration files for all of the stored profiles. The Native PHY also checks your multiple reconfiguration profiles for consistency to ensure you can reconfigure between them. Among other things this checks that you have exposed the same ports for each configuration.14 |
Enable embedded reconfiguration streamer | On/Off | Enables the embedded reconfiguration streamer, which automates the dynamic reconfiguration process between multiple predefined configuration profiles. This is optional and increases logic utilization. The PHY includes all of the logic and data necessary to dynamically reconfigure between pre-configured profiles. |
Generate reduced reconfiguration files | On/Off | When enabled, The Native PHY generates reconfiguration report files containing only the attributes or RAM data that are different between the multiple configured profiles. The reconfiguration time decreases with the use of reduced .mif files. |
Number of reconfiguration profiles | 1-8 | Specifies the number of reconfiguration profiles to support when multiple reconfiguration profiles are enabled. |
Selected reconfiguration profile | 0-7 | Selects which reconfiguration profile to store/load/clear/refresh, when clicking the relevant button for the selected profile. |
Store configuration to selected profile | - | Clicking this button saves or stores the current Native PHY parameter settings to the profile specified by the Selected reconfiguration profile parameter. |
Load configuration from selected profile | - | Clicking this button loads the current Native PHY with parameter settings from the stored profile specified by the Selected reconfiguration profile parameter. |
Clear selected profile | - | Clicking this button clears or erases the stored Native PHY parameter settings for the profile specified by the Selected reconfiguration profile parameter. An empty profile defaults to the current parameter settings of the Native PHY. |
Clear all profiles | - | Clicking this button clears the Native PHY parameter settings for all the profiles. |
Refresh selected profile | - | Clicking this button is equivalent to clicking the Load configuration from selected profile and Store configuration to selected profile buttons in sequence. This operation loads the Native PHY parameter settings from stored profile specified by the Selected reconfiguration profile parameter and subsequently stores or saves the parameters back to the profile. |
Parameter | Value | Description |
---|---|---|
TX Analog PMA Settings | ||
Analog Mode (Load Intel-recommended Default settings) | Cei_11100_lr to xfp_9950 | Selects the analog protocol mode to pre-select the TX pin swing settings (VOD, Pre-emphasis, and Slew Rate). After loading the pre-selected values in the GUI, if one or more of the individual TX pin swing settings need to be changed, then enable the option to override the Intel-recommended defaults to individually modify the settings. |
Override Intel-recommended Analog Mode Default settings | On/Off | Enables the option to override the Intel-recommended settings for the selected TX Analog Mode for one or more TX analog parameters. |
Output Swing Level (VOD) | 0-31 | Selects the transmitter programmable output differential voltage swing. |
Pre-Emphasis First Pre-Tap Polarity | Fir_pre_1t_neg Fir_pre_1t_pos |
Selects the polarity of the first pre-tap for pre-emphasis. |
Pre-Emphasis First Pre-Tap Magnitude | 0-16 15 | Selects the magnitude of the first pre-tap for pre-emphasis |
Pre-Emphasis Second Pre-Tap Polarity | Fir_pre_2t_neg Fir_pre_2t_pos |
Selects the polarity of the second pre-tap for pre-emphasis. |
Pre-Emphasis Second Pre-Tap Magnitude | 0-7 16 | Selects the magnitude of the second pre-tap for pre-emphasis. |
Pre-Emphasis First Post-Tap Polarity | Fir_post_1t_neg Fir_post_1t_pos |
Selects the polarity of the first post-tap for pre-emphasis |
Pre-Emphasis First Post-Tap Magnitude | 0-25 17 | Selects the magnitude of the first post-tap for pre-emphasis. |
Pre-Emphasis Second Post-Tap Polarity | Fir_post_2t_neg Fir_post_2t_pos |
Selects the polarity of the second post-tap for pre-emphasis. |
Pre-Emphasis Second Post-Tap Magnitude | 0-12 18 | Selects the magnitude of the second post-tap for pre-emphasis |
Slew Rate Control | slew_r0 to slew_r5 | Selects the slew rate of the TX output signal. Valid values span from slowest to the fastest rate. |
High-Speed Compensation | Enable/Disable | Enables the power-distribution network (PDN) induced inter-symbol interference (ISI) compensation in the TX driver. When enabled, it reduces the PDN induced ISI jitter, but increases the power consumption. |
On-Chip termination | r_r1 r_r2 |
Selects the on-chip TX differential termination. |
RX Analog PMA Settings | ||
Override Intel-recommended Default settings | On/Off | Enables the option to override the Intel-recommended settings for one or more RX analog parameters |
CTLE (Continuous Time Linear Equalizer) mode | non_s1_mode |
Selects the RX high gain mode non_s1_mode for the Continuous Time Linear Equalizer (CTLE). |
DC gain control of high gain mode CTLE | No_dc_gain to stg4_gain7 | Selects the DC gain of the Continuous Time Linear Equalizer (CTLE) in high gain mode |
AC Gain Control of High Gain Mode CTLE | radp_ctle_acgain_4s_0 to radp_ctle_acgain_4s_28 | Selects the AC gain of the Continuous Time Linear Equalizer (CTLE) in high gain mode when CTLE is in manual mode. |
Variable Gain Amplifier (VGA) Voltage Swing Select | radp_vga_sel_0 to radp_vga_sel_4 | Selects the Variable Gain Amplifier (VGA) output voltage swing. |
On-Chip termination | R_ext0, r_r1, r_r2 | Selects the on-chip RX differential termination. |
Parameter | Value | Description |
---|---|---|
Generate parameter documentation file | On/Off | When you turn on this option, generation produces a Comma-Separated Value (.csv ) file with descriptions of the Transceiver Native PHY IP parameters. |
14 For more information on timing closure, refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter.
15 For more information refer to Available Options table in the XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T section of the Analog Parameter Settings chapter.
16 For more information refer to Available Options table in the XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T section of the Analog Parameter Settings chapter.
17 For more information refer to Available Options table in the XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP section of the Analog Parameter Settings chapter.
18 For more information refer to Available Options table in the XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP section of the Analog Parameter Settings chapter.