Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Public
Document Table of Contents

1.8.1. Using an Exported Partition to Send to a Design Without Including Source Files

Scenario background: A designer wants to produce a design block and needs to send out their design, but to preserve their IP, they prefer to send a synthesized netlist instead of providing the HDL source code to the recipient. You can use this flow to implement a black box.

Use this flow to package a full design as a single source file to send to an end customer or another design location.

As the sender in this scenario perform the following steps to export a design block:

  1. Provide the device family name to the recipient. If you send placement information with the synthesized netlist, also provide the exact device selection so they can set up their project to match.
  2. Create a black box wrapper file that defines the port interface for the design block and provide it to the recipient for instantiating the block as an empty partition in the top-level design.
  3. Create a Intel® Quartus® Prime project for the design block, and complete the design.
  4. Export the level of hierarchy into a single .qxp. Following a successful compilation of the project, you can generate a .qxp from the GUI, the command-line, or with Tcl commands, as described in the following:
    • If you are using the Intel® Quartus® Prime GUI, use the Export Design Partition dialog box.
    • If you are using command-line executables, run quartus_cdb with the --incremental_compilation_export option.
    • If you are using Tcl commands, use the following command: execute_flow -incremental_compilation_export.
  5. Select the option to include just the Post-synthesis netlist if you do not have to send placement information. If the recipient wants to reproduce your exact Fitter results, you can select the Post-fitting netlist option, and optionally enable Export routing.
  6. If a partition contains sub-partitions, then the sub-partitions are automatically flattened and merged into the partition netlist before exporting. You can change this behavior and preserve the sub-partition hierarchy by turning off the Flatten sub-partitions option on the Export Design Partition dialog box. Optionally, you can use the -dont_flatten sub-option for the export_partition Tcl command.
  7. Provide the .qxp to the recipient. Note that you do not have to send any of your design source code.

As the recipient in this example, first create a Intel® Quartus® Prime project for your top-level design and ensure that your project targets the same device (or at least the same device family if the .qxp does not include placement information), as specified by the IP designer sending the design block. Instantiate the design block using the port information provided, and then incorporate the design block into a top‑level design.

Add the .qxp from the IP designer as a source file in your Intel® Quartus® Prime project to replace any empty wrapper file. If you want to use just the post-synthesis information, you can choose whether you want the file to be a partition in the top‑level design. To use the post-fit information from the .qxp, assign the instance as a design partition and set the netlist type to Post-Fit.