F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP

The JTAG to Avalon Master Bridge Intel FPGA IP provides access to the reconfiguration register space of the F-tile through System Console. The Intel® Quartus® Prime software inserts the debug interconnect fabric to connect the JTAG interface to the PMA.

To Enable the JTAG to Avalon Master Bridge Intel FPGA IP Interface

  1. Enable the Enable datapath Avalon interface and Enable PMA Avalon interface options in the Avalon Memory-Mapped Interface tab of the F-Tile PMA/FEC Direct PHY Intel® FPGA IP parameter editor.
  2. Enable the Enable readdatavalid port on datapath Avalon interface and Enable readdatavalid port on PMA Avalon interface options in the Avalon Memory-Mapped Interface tab of the F-Tile PMA/FEC Direct PHY Intel® FPGA IP parameter editor.
    Figure 84. IP Parameter Editor
  3. Instantiate two JTAG to Avalon Master Bridge Intel FPGA IP instances from the IP Catalog. The first instance to interface with datapath Avalon® interface, and the second instance to interface with the PMA Avalon® interface.
    Figure 85. IP Catalog
  4. Connect the clock and reset signals to the reconfig_pdp_clk and reconfig_pdp_reset ports of the datapath reconfiguration interface.
  5. Connect the other datapath reconfiguration interface signals:
    • reconfig_pdp_write
    • reconfig_pdp_read
    • reconfig_pdp_address
    • reconfig_pdp_writedata
    • reconfig_pdp_readdata
    • reconfig_pdp_byteenable
    • reconfig_pdp_readdatavalid
    • reconfig_pdp_waitrequest
    To the equivalent JTAG to Avalon Master Bridge Intel FPGA IP reconfiguration signals.
  6. Follow the same connection guidelines as in steps 4 and 5 for the reconfig_xcvr* PMA interface signals.

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