F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.4.5. Custom Cadence Control and Status Signals

Table 42.  Custom Cadence Control and Status Signals
Signal Name Clocks Domain/Resets Direction Description
tx_cadence

tx_cadence_fast_clk

tx_reset

output Indicates the rate at which data_valid pin must be asserted and deasserted when the system is running at a higher clock rate than the PMA word/bond clock. Use this signal to assert and de-assert the TX PMA Interface data valid bit when custom cadence generation ports and logic is enabled. Refer to Parallel Data Mapping Information.
tx_cadence_fast_clk N/A input Fast clock input for tx_cadence generator. Use this as the system clock within F-tile (or use (system clock)/2 when Core Interface is in double width mode). Refer to Custom Cadence Generation Ports and Logic.
tx_cadence_slow_clk N/A input Slow clock input for tx_cadence generator. Use this clock as the PMA word/bond clock (or (PMA word/bond clock)/2 when Core Interface is in double width mode). Refer to Custom Cadence Generation Ports and Logic.
tx_cadence_slow_clk_locked N/A input By default, CCG logic assumes tx_cadence_slow_clk_locked is coming from TX PLL, and uses tx_pll_locked to deassert CGG logic reset. However, if tx_cadence_slow_clk is not directly coming from the TX PLL word clock/bond clock/user clock), but rather comes from other clock source, then you must turn on the tx_cadence_slow_clk_locked port option in the parameter editor. tx_cadence_slow_clk_locked must be driven by the PLL locked output of the other clock source used for slow clock.

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