F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1)

The following data is specific to the X=1 case. N indicates the number of PMA lanes. For a given N, n can be from 0 --> N-1. N can be up to 16 for FGT, and up to 4 for FHT, and depends on the number of PMA lanes and PMA width configuration. Enable Double width transfer = 0. Refer to Table 1 for full variable definitions.

Table 61.  Example of TX Parallel Data bits for PMA Width = 8, 10, 16, 20, 32 (X=1)
Bits TX Parallel Data for n=0 Bits TX Parallel Data for n=1 ●● Bits TX Parallel Data for n=15
79 Write Enable for TX Core FIFO in Elastic Mode 159 Write Enable for TX Core FIFO in Elastic Mode ●●● 1279 Write Enable for TX Core FIFO in Elastic Mode
38 TX PMA Interface Data Valid 118 TX PMA Interface Data Valid 1238 TX PMA Interface Data Valid
31:0 TX Data 111:80 TX Data 1231:1200 TX Data

The following are the TX PMA Interface Data Valid signals for each of the PMA Lanes in Table 61:

  • If N=1, tx_parallel_data [38]
  • If N=2, tx_parallel_data [118]

..

  • If N=16, tx_parallel_data [1238]

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