F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.13.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface

The following examples show the RTL connections for a single PMA channel with clock and reset connections and no FPGA core logic driving the additional reconfiguration ports.

Example datapath reconfiguration interface connections for a 16 PMA lanes design:

.reconfig_pdp_clk           ( 100MHz         ),
.reconfig_pdp_reset         ( reconfig_reset ),
.reconfig_pdp_write         ( 1’b0           ),
.reconfig_pdp_read          ( 1’b0           ), 
.reconfig_pdp_address       ( 18’b0          ),
.reconfig_pdp_byteenable    ( 4’b0	       ),
.reconfig_pdp_writedata     ( 32’b0          ),
.reconfig_pdp_readdata      ( ),
.reconfig_pdp_waitrequest   ( )

Example PMA reconfiguration interface connections for a 16 PMA lanes design:

.reconfig_xcvr_clk         ( 100MHz         ),   
.reconfig_xcvr_reset       ( reconfig_reset ),
.reconfig_xcvr_write       ( 1’b0           ),
.reconfig_xcvr_read        ( 1’b0           ),
.reconfig_xcvr_address     ( 22’b0          ),
.reconfig_xcvr_byteenable  ( 4’b0           ),
.reconfig_xcvr_writedata   ( 32’b0          ),
.reconfig_xcvr_readdata    ( ),
.reconfig_xcvr_waitrequest ( )

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