F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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2.2.5.2. Topology 14: 1x PCIe x4 + 400G Hard IP (FGT) with PTP Example

This example assumes the following design considerations for an F-tile:

  • A PCIe* interface is required.
  • An IEEE 1588 precision time protocol interface is required.
  • FHT PMA lanes are not required.

Topology 12: 1x PCIe x8 + 400G Hard IP (FGT) with PTP , Topology 13: 2x PCIe x4 + 400G Hard IP (FGT) with PTP , and Topology 14: 1x PCIe x4 + 400G Hard IP (FGT) with PTP can implement this design. Select Topology 14: 1x PCIe x4 + 400G Hard IP (FGT) with PTP because it has the most available PMAs and streams. The following figure shows the PMA, fracture, and EMIB resource availability.

Figure 32.  Topology 14: 1x PCIe x4 + 400G Hard IP (FGT) with PTP

Legend

  • Gray: unavailable resource
  • Light blue: available 400G hard IP resource
  • Purple: available PTP resource
  • Dark blue: available PCIe* hard IP resource

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