F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.4.10. Datapath Avalon® Memory Mapped Interface Signals

Table 48.  Datapath Avalon® Memory Mapped Interface Signals (Enable Separate Avalon® Interface per Fracture = 0)Refer to Table 1 for variable definitions.
Signal Name Clocks Domain/Resets Direction Description
reconfig_pdp_clk Clock Input Reconfig Interface Clock
reconfig_pdp_reset reconfig_pdp_clk Input Reconfiguration Interface Reset
reconfig_pdp_address[13+K d :0] reconfig_pdp_clk Input Reconfig Interface Address. Word address. EMIB core adapter and soft CSR registers use unused space of F-tile Datapath Avalon® memory mapped 16-bit address. Refer to for Kd values.
reconfig_pdp_byteenable [3:0] reconfig_pdp_clk Input Byte Enable. If byteenable[3:0] is 4’b1111, 32-bit Dword Access is assumed; otherwise byte access is used.
reconfig_pdp_write reconfig_pdp_clk Input Reconfig Write
reconfig_pdp_read reconfig_pdp_clk Input Reconfig Read
reconfig_pdp_writedata [31:0] reconfig_pdp_clk Input Reconfig Writedata
reconfig_pdp_readdata [31:0] reconfig_pdp_clk Output Reconfig Read data
reconfig_pdp_waitrequest reconfig_pdp_clk Output Reconfig Wait Request
reconfig_pdp_readdatavalid reconfig_pdp_clk Output Reconfig Read Data Valid. Optional port, available if the port is enabled in parameter editor.
Table 49.  Datapath Avalon® Memory Mapped Interface Signals (Enable Separate Avalon® Interface per fracture = 1)Refer to Table 1 for variable definitions.
Signal Name Clocks Domain/Resets Direction Description
reconfig_pdp<n>_clk Clock Input Reconfig Interface Clock
reconfig_pdp<n>_reset_st<n> reconfig_pdp<n>_clk Input Reconfig Interface Reset
reconfig_pdp<n>_address[13:0] reconfig_pdp<n>_clk Input Reconfig Interface Address. EMIB core adapter and soft CSR registers use unused space of F-tile Datapath. Avalon® memory mapped 16-bit address. Soft CSR is only at _pdp0_ interface for single system IP.
reconfig_pdp<n>_byteenable [3:0] reconfig_pdp<n>_clk Input Byte Enable. If byteenable[3:0] is 4’b1111, uses 32-bit Dword Access; otherwise uses byte access.
reconfig_pdp<n>_write_st reconfig_pdp<n>_clk Input Reconfig Write
reconfig_pdp<n>_read_st reconfig_pdp<n>_clk Input Reconfig Read
reconfig_pdp<n>_writedata[31:0] reconfig_pdp<n>_clk Input Reconfig Writedata
reconfig_pdp<n>_readdata[31:0] reconfig_pdp<n>_clk Output Reconfig Read data
reconfig_pdp<n>_waitrequest reconfig_pdp<n>_clk Output Reconfig Wait Request
reconfig_pdp<n>_readdatavalid reconfig_pdp<n>_clk Output Reconfig Read Data Valid. Optional port, available if the port is enabled on the GUI.

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