6.2.3. Setting RX Datapath Options
Specify options for the following on the F-Tile PMA/FEC Direct PHY Intel® FPGA IP parameter editor RX Datapath Options tab:
- RX FGT CDR
- RX datapath FIFO modes
The design specifies the following RX Datapath Options:
|RX FGT CDR reference clock frequency||Select 156.25MHz. The RX FGT CDR reference clock frequency must match the reference clock frequency that the F-Tile Reference and System PLL Clocks Intel® FPGA IP specifies. To connect the out_refclk_fgt_0 to this IP, refer to Connecting the F-tile PMA/FEC Direct PHY Design IP|
|RX PMA interface FIFO mode||Elastic|
|RX core Interface FIFO Mode||Phase Compensation|
|Enable RX double width transfer||On
Note: When you enable this option, you must drive the tx_clkout source with Sys PLL Clk Div2 source instead of sys PLL clk source. Divide the core clocking frequency by two in this way to avoid exceeding the maximum EMIB to core frequency specification.
The RX F-tile Interface FIFO mode is always designed to be in Register mode for PMA direct mode, and you cannot select a different option for this IP.
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