F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.4.10.1. Number of Datapath Memory Mapped Avalon® Interfaces and Additional Address Bits per Interface

Table 50.  Number of Datapath Memory Mapped Avalon® Interfaces and Additional Address Bits per InterfaceRefer to Table 1 for variable definitions.
FEC Enabled Split Interface Enabled26 Number of Avalon® interfaces Additional Address Bits for Decoding (K d )
0 0 1 K d =Ceiling(log2(N))
0 1 N K d =0
1 X 1 K d =0
26 Split Interface for datapath Memory mapped Avalon interface only supported for PMA Direct mode.

Did you find the information on this page useful?

Characters remaining:

Feedback Message