F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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6.8. F-tile Interface Planning

The decomposable Intel® Agilex™ F-tile architecture prompts a new tile planning step for PHY layer implementation. This step allows you to place component IP in specific device tiles to reflect your board or system level constraints. The Intel® Quartus® Prime Tile Interface Planner simplifies placement of component IP in legal tile locations.

Tile Interface Planner displays your design's component IP in a hierarchical view, next to a visual display of the device tile fractures. You locate legal tile locations, place the IP, and save the placement constraints for downstream Compiler stages. The legality engine verifies placement in real-time to ensure correlation in final implementation.

Figure 106. Tile Interface Planner

Tile Interface Planner guides you through the tile planning steps:

Figure 107. Tile Interface Planner Tool Flow

Refer to Tile Interface Planning in the Intel® Quartus® Prime Pro Edition User Guide: Design Constraints for Tile Interface Planner use information.

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