F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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6.5. Enabling Custom Cadence Generation Ports and Logic

This F-tile PMA/FEC Direct PHY design uses System PLL clocking mode to clock the digital datapath of the FGT PMA lane. Because the system PLL frequency (830.078125MHz) is greater than the PMA clock frequency (805.6640625MHz), you must enable custom cadence generation logic ports, and enable the logic option in the IP parameter editor.

  • You must use tx_cadence port output to assert and de-assert the TX PMA Interface data valid bit (one of the bits in TX parallel data). Refer to Parallel Data Mapping Information.
  • You must connect tx_cadence_fast_clk to tx_clkout/tx_clkout2 with clock source System PLL Clock / 2 (415.0390625MHz).
  • You must connect tx_cadence_slow_clk to tx_clkout/tx_clkout2 with clock source Word clock or Bond clock / 2 (402.83203125 MHz)
Figure 104. Enabling Custom Cadence Generation Ports and Logic

Rate Match FIFO Requirement

The following guidelines apply to the elastic FIFO requirement between user FPGA core logic and the F-Tile PMA/FEC Direct PHY Intel® FPGA IP:

  • If the user FPGA core logic is running at same frequency as system PLL frequency/2 (that is, 415.0390625MHz), then there is no elastic FIFO requirement between the user FPGA core logic and the F-Tile PMA/FEC Direct PHY Intel® FPGA IP.
  • If the user FPGA core logic is running at PMA clock frequency/2 (that is, 402.83203125 MHz), this requires elastic FIFO between the user FPGA core logic and the F-tile core interface FIFO to transfer from PMA clock frequency domain to system PLL clock frequency domain and must be implemented by the user.

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