F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations

The following show the TX and RX parallel data mapping information for different configurations, using the calculations from Parallel Data Mapping information for TX and RX. Refer to Table 1 for full variable definitions.

Table 59.  TX and RX Parallel Data Mapping Information (PMA Lanes, N = 1) Table Notes:
  1. For unused bits, you can tie the signal to '0' or '1' or leave it unconnected.
  2. The core interface FIFO TX Write Enable and RX Data Valid signal is only valid when you are using PMA clocking mode, and when the core FIFO is in elastic mode.
  3. The TX and RX PMA interface data valid signal is only valid when you are using System PLL clocking mode.
PMA Configuration Bits TX Parallel Data RX Parallel Data

FGT

PMA Width = 8, 10, 16, 20, 32

Single Width

(One PMA Lane [N=1] with PMA Width ≤ 32)

FHT

PMA Width = 32

Single Width

79 Write Enable for TX Core FIFO in Elastic Mode Data valid for RX Core FIFO in Elastic Mode
38 TX PMA Interface Data Valid RX PMA Interface Data Valid
[D-1]:0 TX Data RX Data

FGT

PMA Width = 8, 10, 16, 20, 32

Double Width

(One PMA Lane [N=1] with PMA Width ≤ 32)

FHT

PMA Width = 32

Double Width

79 Write Enable for TX Core FIFO in Elastic Mode Data Valid for RX Core FIFO in Elastic Mode
[D -1 + 40]:40 TX Data (Upper Data Bits) RX Data (Upper Data Bits)
38 TX PMA Interface Data Valid RX PMA Interface Data Valid
[D -1]:0 TX Data (Lower Data Bits) RX Data (Lower Data Bits)

FGT/FHT

PMA Width = 64

Double Width

(One PMA Lane [N=1] with PMA Width = 64)

Second Stream

159 Write Enable for TX Core FIFO in Elastic Mode Data Valid for RX Core FIFO in Elastic Mode
158   RX Deskew
151:120 TX Data (Upper Data Bits) RX Data (Upper Data Bits)
118 TX PMA Interface Data Valid RX PMA Interface Data Valid
111:80 TX Data (Lower Data Bits) RX Data (Lower Data Bits)
First Stream 79 Write Enable for TX Core FIFO in Elastic Mode Data Valid for RX Core FIFO in Elastic Mode
78   RX Deskew
71:40 TX Data (Upper Data Bits) RX Data (Upper Data Bits)
38 TX PMA Interface Data Valid RX PMA Interface Data Valid
31:0 TX Data (Lower Data Bits) RX Data (Lower Data Bits)

FHT

PMA Width = 128

Double Width

(One PMA Lane [ N =1] with PMA Width = 128 )

Fourth Stream

319 Write Enable for TX Core FIFO in Elastic Mode Data valid for RX Core FIFO in Elastic Mode
318   RX Deskew
311:280 TX Data (Upper Data Bits) RX Data (Upper Data Bits)
278 TX PMA Interface Data Valid RX PMA Interface Data Valid
271:240 TX Data (Lower Data Bits) RX Data (Lower Data Bits)
Third Stream 239 Write Enable for TX Core FIFO in Elastic Mode Data valid for RX Core FIFO in Elastic Mode
238   RX Deskew
231:200 TX Data (Upper Data Bits) RX Data (Upper Data Bits)
198 TX PMA Interface Data Valid RX PMA Interface Data Valid
191:160 TX Data (Lower Data Bits) RX Data (Lower Data Bits)
Second Stream 159 Write Enable for TX Core FIFO in Elastic Mode Data valid for RX Core FIFO in Elastic Mode
158   RX Deskew
151:120 TX Data (Upper Data Bits) RX Data (Upper Data Bits)
118 TX PMA Interface Data Valid RX PMA Interface Data Valid
111:80 TX Data (Lower Data Bits) RX Data (Lower Data Bits)
First Stream 79 Write Enable for TX Core FIFO in Elastic Mode Data valid for RX Core FIFO in Elastic Mode
78   RX Deskew
71:40 TX Data (Upper Data Bits) RX Data (Upper Data Bits)
38 TX PMA Interface Data Valid RX PMA Interface Data Valid
31:0 TX Data (Lower Data Bits)

RX Data (Lower Data Bits)

Table 60.  TX and RX Parallel Data Mapping Information (Number of PMA Lanes (N) = 1)
PMA Configuration Bits TX Parallel Data RX Parallel Data

FEC

FGT/FHT

One PMA Lane (N)=1

Total Streams = 1

PMA Width = 32

First stream

77 Alignment Marker -
72:40 TX Data (Upper 33 bits) RX Data (Upper 33 Bits)
38 TX PMA Interface Data Valid Bit RX PMA Interface Data Valid Bit
37 Alignment Marker Alignment Marker
32:2 TX Data (Lower 31 Bits) RX Data (Lower 31 Bits)
1:0 Sync Head Sync Head

FEC

FGT/FHT

One PMA Lane (N) = 1

Total Streams = 2

PMA Width = 64

Second Stream

158 - RX Deskew Bit
157 Alignment Marker -
152:120 TX Data (Upper 33 bits) RX Data (Upper 33 Bits)
118 TX PMA Interface Data Valid Bit -
117 Alignment Marker -
112:82 TX Data (lower 31 bits) RX Data (lower 31 bits)
81:80 Sync Head Sync Head

First stream

78 - RX Deskew Bit
77 Alignment Marker -
72:40 TX Data (Upper 33 Bits) RX Data (Upper 33 Bits)
38 TX PMA Interface Data Valid Bit RX PMA Interface Data Valid Bit
37 Alignment Marker Alignment Marker
32:2 TX Data (Lower 31 Bits) RX Data (Lower 31 Bits)
1:0 Sync Head Sync Head

FEC

FHT

One PMA Lane(N) =1

Total Streams = 4

PMA Width = 128

Fourth Stream

318 - RX Deskew Bit
317 Alignment marker -
312:280 TX Data (Upper 33 Bits) RX Data (Upper 33 Bits)
278 TX PMA Interface Data Valid Bit -
277 Alignment Marker -
272:242 TX Data (Lower 31 Bits) RX Data (Lower 31 Bits)
241:240 Sync Head Sync Head

Third Stream

238 - RX Deskew Bit
237 Alignment Marker -
232:200 TX Data (Upper 33 Bits) RX Data (Upper 33 Bits)
198 TX PMA Interface Data Valid Bit -
197 Alignment Marker -
192:162 TX Data (Lower 31 Bits) RX Data (Lower 31 Bits)
161:160 Sync Head Sync Head

Second Stream

158 RX Deskew Bit
157 Alignment Marker -
152:120 TX Data (Upper 33 Bits) RX Data (upper 33 Bits)
118 TX PMA Interface Data Valid Bit -
117 Alignment Marker -
112:82 TX Data (Lower 31 Bits) RX Data (Lower 31 Bits)
81:80 Sync Head Sync Head

First stream

78 - RX Deskew Bit
77 Alignment Marker -
72:40 TX Data (Upper 33 Bits) RX Data (Upper 33 Bits)
38 TX PMA Interface Data Valid Bit RX PMA Interface Data Valid Bit
37 Alignment Marker Alignment Marker
32:2 TX Data (Lower 31 Bits) RX Data (Lower 31 Bits)
1:0 Sync Head Sync Head

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