F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.11.3. FGT PMA Register Map

The FGT PMA Register Map contains the PMA analog registers, TX PLL counter registers, debug and loopback register information for the FGT lanes.

You must enable the Enable PMA Avalon® interface setting under the PMA Avalon® Memory-Mapped Interface section in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP parameter editor to access the FGT PMA registers.

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