F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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Document Table of Contents

2.2.5.1. Topology 5: 400G Hard IP (FHT) + 200G Hard IP (FGT) Example

This example assumes the following design considerations for an F-tile:

  • A PCIe* interface is not required.
  • An IEEE 1588 precision time protocol interface is not required.
  • FHT PMA lanes are required.

Topology 5: 400G Hard IP (FHT) + 200G Hard IP (FGT) is the only way to implement this design. The following figure shows the PMA, fracture, and EMIB resource availability.

Figure 31.  Topology 5: 400G Hard IP (FHT) + 200G Hard IP (FGT)

Legend

  • Gray: unavailable resource
  • Light blue: available 400G hard IP resource
  • Green: available 200G hard IP resource

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