F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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2.4.1.1. FHT Reference Clock Network

There are two reference clocks (refclk[0] and refclk[1]) for FHT PMAs, both accessible by any of the four FHT PMAs. refclk[0] and refclk[1] can be different frequencies. The frequency range is 100-200 MHz, and it is a continuous range.

As shown in Figure 46, FHT has six PLLs.

  • Two common PLLs connected to all four lanes: PLL A and PLL B
  • Four lane PLLs, one PLL per lane for all four lanes: TX PLL

To optimize performance, FHT has a cascaded PLL scheme between common PLLs and lane PLLs, the common PLLs providing a cleaner clock to the lane PLLs.

  • Common PLLs and lane PLLs support integer and fractional modes. However, a common PLL cannot be in fractional mode when the corresponding lane PLL is in fractional mode. See the following table.
  • One common PLL drives the microcontroller. The reference clock that drives this common PLL must be present and stable throughout F-tile operation.
  • Common PLLs generate two clock frequencies (100 and 156.25 MHz) which go to the lane PLLs. One of them must be selected to drive the lane PLLs.
Table 19.  Supported Combinations of Lane PLL and Common PLL Modes
Lane PLL Mode Corresponding Common PLL Mode Supported or Not Supported
Integer Integer Supported
Integer Fractional Supported
Fractional Integer Supported
Fractional Fractional Not supported
Figure 46. FHT Reference Clock Network
Table 20.  FHT Reference Clocks
FHT Reference Clocks Direction Accessible FHT PMA Accessible to System PLLs?
refclk[0] Input FHT0, FHT1, FHT2, FHT3 No
refclk[1] Input FHT0, FHT1, FHT2, FHT3 No

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