F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.4.9. PMA Avalon® Memory Mapped Interface Signals

Table 46.  PMA Avalon® Memory Mapped Interface Signals (Enable Separate Avalon® Interface per PMA = 0)Refer to Table 1 for full variable definitions.
Signal Name Clocks Domain/Resets Direction Description
reconfig_xcvr_clk Clock Input Reconfig Interface Clock
reconfig_xcvr_reset reconfig_xcvr_clk Input Reconfig Interface Reset
reconfig_xcvr_address[17+K p:0] reconfig_xcvr_clk Input Reconfig Interface Address K p=Ceiling(log2(N)). Upper address bits are for shared PMA decoding if more than one PMA exists.
reconfig_xcvr_byteenable [3:0] reconfig_xcvr_clk Input Byte Enable. If byteenable[3:0] is 4’b1111, uses 32-bit Dword Access; otherwise uses byte access.
reconfig_xcvr_write reconfig_xcvr_clk Input Reconfig Write
reconfig_xcvr_read reconfig_xcvr_clk Input Reconfig Read
reconfig_xcvr_writedata [31:0] reconfig_xcvr_clk Input Reconfig Write data
reconfig_xcvr_readdata [31:0] reconfig_xcvr_clk Output Reconfig Read data
reconfig_xcvr_waitrequest reconfig_xcvr_clk Output Reconfig Wait Request
reconfig_xcvr_readdatavalid reconfig_xcvr_clk Output Reconfig Read Data Valid. Optional port, available if the port is enabled in parameter editor.
Table 47.  PMA Avalon® Memory Mapped Interface Signals (Enable Separate Avalon® Interface per PMA = 1 )Refer to Table 1 for variable definitions.
Signal Name Clocks Domain/Resets Direction Description
reconfig_xcvr<n>_clk Clock Input Reconfig Interface Clock
reconfig_xcvr<n>_reset reconfig_xcvr<n>_clk Input Reconfig Interface Reset
reconfig_xcvr<n>_address[17:0] reconfig_xcvr<n>_clk Input Upper address bits are for shared PMA decoding if more than 1 PMA exists.
reconfig_xcvr<n>_byteenable [3:0] reconfig_xcvr<n>_clk Input Byte Enable. If byteenable[3:0] is 4’b1111, uses 32-bit Dword; otherwise uses byte access.
reconfig_xcvr<n>_write reconfig_xcvr<n>_clk Input Reconfig Write
reconfig_xcvr<n>_read reconfig_xcvr<n>_clk Input Reconfig Read
reconfig_xcvr<n>_writedata [31:0] reconfig_xcvr<n>_clk Input Reconfig Write data
reconfig_xcvr<n>_readdata [31:0] reconfig_xcvr<n>_clk Output Reconfig Read data
reconfig_xcvr<n>_waitrequest reconfig_xcvr<n>_clk Output Reconfig Wait Request
reconfig_xcvr<n>_readdatavalid reconfig_xcvr<n>_clk Output Reconfig Read Data Valid. Optional port, available if the port is enabled in parameter editor.

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