F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.8.5. Status Signals—Descriptions

Table 75.  Status Signal DescriptionsRefer to Table 1 for variable definitions.
Name Width Domain Direction Type Description
tx_pll_locked [N-1:0] N Asynchronous Output Direct TX channel PLL locked signal for both FGT and FHT to reference clock within the PPM threshold status signal for fast/medium or slow PLL. 1’b1 = locked. 1’b0 = not locked.
rx_is_lockedtoref [N-1:0] N Asynchronous Output Direct

CDR lock status signal.

  • 1’b1 – CDR is frequency locked to reference clock within the PPM threshold.
  • 1’b0 – CDR is not frequency locked within the PPM threshold.

Applicable to FGT PMA only. When lockedtodata stays high, the lockedtoref signal status is insignificant.

rx_is_lockedtodata [N-1:0] N Asynchronous Output Direct RX CDR data lock status signal.
  • 1’b0: CDR is not locked to data.
  • 1’b1: CDR is locked to data. Applicable to both FGT and FHT PMA.

When asserted, indicates that the CDR is in locked-to-data mode. When continuously asserted and does not switch between asserted and deasserted, you can confirm that the CDR is actually locked to data.

Did you find the information on this page useful?

Characters remaining:

Feedback Message