F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.4.3. Reset Signals

Table 40.  Reset Signals
Signal Name Clocks Domains Direction Description
tx_reset asynchronous input TX reset input for TX PMA and TX datapath. Must asserted until tx_reset_ack is asserted.
rx_reset asynchronous input RX reset input for RX PMA and RX datapath. Must be kept asserted until rx_reset_ack is asserted.
tx_reset_ack asynchronous output TX fully in reset indicator.
rx_reset_ack asynchronous output RX fully in reset indicator.
tx_am_gen_start asynchronous output When using FEC, indicates when to start sending alignment markers. This clears once tx_am_gen_2x_ack is asserted.
tx_am_gen_2x_ack asynchronous input When using FEC, indicates to the reset sequencer at least 2 alignment markers were sent since tx_am_gen_start is asserted. This signal is deasserted after tx_am_gen_start is deasserted.
tx_ready asynchronous output Status port to indicate when TX PMA and TX datapath are reset successfully and ready for data transfer.
rx_ready asynchronous output

If RX de-skew is disabled:

Status port to indicate when RX PMA and RX datapath are reset successfully and ready for data transfer.

If RX de-skew is enabled:

Status port to indicate when RX PMA and RX datapath are reset successfully, RX de-skew is done, and ready for data transfer.

Did you find the information on this page useful?

Characters remaining:

Feedback Message