F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP

The F-Tile PMA/FEC Direct PHY Intel® FPGA IP is the primary IP component for PMA and FEC direct usage. This IP provides direct access to the F-tile PMA block features for both FGT and FHT.

To customize and instantiate the IP for your protocol implementation, you specify parameter values for the F-Tile PMA/FEC Direct PHY Intel® FPGA IP and generate the IP RTL and supporting files from the Intel® Quartus® Prime parameter editor. The top-level file generated with the IP instance includes all the available ports for your configuration.

You can use the F-Tile PMA/FEC Direct PHY Intel® FPGA IP in your design if a custom PCS or MAC block is created using your own logic, rather than using the Intel FPGA PCS or MAC block.

The F-Tile PMA/FEC Direct PHY Intel® FPGA IP allows you to configure the F-tile FGT and FHT to support PMA and FEC direct modes with the following:

  • Predefined preset parameters for IP
  • Datapath Clocking mode, PMA type, PMA modulation type, PMA data rate
  • TX datapath and RX Datapath options settings (FIFO modes, TX PLL, RX CDR)
  • RS-FEC Modes and options
  • Datapath Avalon® Memory Mapped Interface, PMA Avalon® Memory Mapped Interface

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