F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.4.8. TX and RX PMA and Core Interface FIFO Signals

Table 45.  TX and RX PMA and Core Interface FIFO SignalsRefer to Table 1 for variable definitions.
Signal Name Clocks Domain/Resets Direction Description
tx_pmaif_fifo_empty [(N*X)-1:0] asynchronous output PMA Interface TX FIFO empty .
tx_pmaif_fifo_pempty [(N*X)-1:0] asynchronous output PMA Interface TX FIFO partially empty.
tx_pmaif_fifo_pfull [(N*X)-1:0] asynchronous output PMA Interface TX FIFO partially full.
rx_pmaif_fifo_empty [(N*X)-1:0] asynchronous output PMA Interface RX FIFO empty.
rx_pmaif_fifo_pempty [(N*X)-1:0] asynchronous output PMA Interface RX FIFO partially empty.
rx_pmaif_fifo_pfull [(N*X)-1:0] asynchronous output PMA Interface RX FIFO partially full.
tx_fifo_full [(N*X)-1:0]

tx_coreclkin

tx_reset

output Core Interface TX FIFO full port.
tx_fifo_empty [(N*X)-1:0]

TX Word Clock

TX Bond Clock

Sys PLL Clock

output Core Interface TX FIFO empty port.
tx_fifo_pfull [(N*X)-1:0]

tx_coreclkin

tx_reset

output Core Interface TX FIFO partially full port.
tx_fifo_pempty [(N*X)-1:0]

TX Word Clock

TX Bond Clock

Sys PLL Clock

output Core Interface TX FIFO partially empty port.
rx_fifo_full [(N*X)-1:0]

Transfer clock:

Word Clock

Bond Clock

Sys PLL Clock

rx_reset

output Core Interface RX FIFO full port.
rx_fifo_empty [(N*X)-1:0]

rx_coreclkin

rx_reset

output Core Interface RX FIFO empty port.
rx_fifo_pfull [(N*X)-1:0]

Transfer clock:

Word Clock

Bond Clock

Sys PLL Clock

rx_reset

output Core Interface RX FIFO partially full port.
rx_fifo_pempty [(N*X)-1:0]

rx_coreclkin

rx_reset

output Core Interface RX FIFO partially empty port.
tx_dll_lock [(N*X)-1:0] tx_reset output TX DLL locked status signal for data transfer. Monitor this signal when the core interface FIFO is in elastic mode, wait for tx_dll_lock port to assert before asserting the write enable bit for the core interface FIFO. Refer to TX and RX Parallel Data Mapping Information for Different Configurations.
rx_fifo_rd_en [(N*X)-1:0]

rx_coreclkin

rx_reset

input Core Interface RX FIFO read enable port.

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