F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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4.2. IP Port List

The following table lists the ports for the IP; all ports are 1-bit wide.

Table 89.   F-Tile Reference and System PLL Clocks Intel® FPGA IP Port ListRefer to refer to for recommended connections.
Port Name Direction Description
FHT
in_refclk_fht_i Input FHT reference clock input port. Must be mapped to device reference clock pin. Maximum of 2 (i = 0 to 1) ports of this type.
out_fht_cmmpll_clk_i Output FHT common PLL output port. Must be connected to protocol IPs, connected to FHT building-block. There can be a maximum of 2(i = 0 to 1) ports of this type.
FGT and System PLL
in_refclk_fgt_i Input FGT and system PLL reference clock input port. Must be mapped to device reference clock pin. This reference clock port can be connected to FGT PMA, system PLL or both. There can be a maximum of 10 (i = 0 to 9) ports of this type.
FGT
out_refclk_fgt_i Output FGT Refclk output port. Must be connected to protocol IPs, connected to FGT building-block. There can be a maximum of 10 (i = 0 to 9) ports of this type.
in_cdrclk_i Input Input port for FGT reference clock configured as CDR output. This must be connected to protocol IP output CDR port. There can be a maximum of 2 (i = 0 to 1) ports of this type.
out_cdrclk_i Output Output port for FGT reference clock configured as CDR output. This must be connected to one of two FGT reference clock pins that can be configured as CDR outputs. You must specify the location assignment in the Intel® Quartus® Prime Pro Edition software qsf settings file for correct functionality. There can be a maximum of 2 (i = 0 to 1) ports of this type.
System PLL
out_systempll_clk_i Output Output port of system PLL. This must be connected to system PLL clock input of protocol IP. There can be a maximum of 3 (i = 0 to 2) ports of this type.
out_systempll_synthlock_i Output System PLL lock status port which indicates if system PLL is locked to incoming reference clock. There can be a maximum of 3 (i = 0 to 2) ports of this type. You can use this port as a status or debug signal.

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