F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.11.6.2. FGT PMA Lane Addressing Example 2

This example demonstrates how to access FGT PMA lane registers in two different F-Tile PMA/FEC Direct PHY Intel® FPGA IP instances.

There are two instances of the F-Tile PMA/FEC Direct PHY Intel® FPGA IP in this example as shown:

  • Instance 1: Two FGT PMA lanes placed in quad 0 at lane 2 and lane 3.
  • Instance 2: Two FGT PMA lanes placed in quad 1 at lane 0 and lane 1.

To access the PMA Avalon memory-mapped interface, you define and control the PMA Avalon memory-mapped interface's address bits (reconfig_xcvr_address[18]) as shown in the following table. The offset address shown are for the FGT TX equalizer settings.

Table 83.  4 FGT Lanes Design with Two Separate F-Tile PMA/FEC Direct PHY Intel® FPGA IP Instances
Quad Lane Logical PMA Avalon® Memory-Mapped Port Index [3:0] Offset Address
0 0 NA 0x47830
1 NA 0x4F830
2 0x0 0x57830
3 0x1 0x5F830
1 0 0x0 0x47830
1 0x1 0x4F830
2 NA 0x57830
3 NA 0x5F830
2 0 NA 0x47830
1 NA 0x4F830
2 NA 0x57830
3 NA 0x5F830
3 0 NA 0x47830
1 NA 0x4F830
2 NA 0x57830
3 NA 0x5F830
If the F-Tile PMA/FEC Direct PHY Intel® FPGA IP has two PMA lanes, there is one additional address bit to set the Avalon® memory-mapped port index value. In this example, it is 0x0 and 0x1. You can use either of these Avalon® memory mapped port index values (0x0 or 0x1) to control any of the two PMA lanes instantiated within the same instance.
For example, you write to the following address to access the registers in that lane:
  • To access quad 1, lane 0, write to 0x047830 or 0x147830.
  • To access quad 0, lane 2, write to 0x057830 or 0x157830.
  • To access quad 0, lane 3, write to 0x05f830 or 0x15f830.
If you configure the PMA lanes within the same F-Tile PMA/FEC Direct PHY Intel® FPGA IP instance, you can use any Avalon® memory mapped port index to access any of the PMA lanes within the same IP instance.

Did you find the information on this page useful?

Characters remaining:

Feedback Message