F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.6.5. FGT Core PLL Mode

You can configure the TX FGT PLL in core PLL mode to use as a clock source for the FPGA. You cannot use the PMA (both TX and RX) for normal operation, when you use the FGT PLL in core PLL mode.

To use the core PLL mode:
  • Select the TX simplex PMA mode.
  • Specify the PMA data rate.
  • Select the TX FGT PLL reference clock frequency.
  • Enable TX user clock 1 or 2.
  • Specify TX user clock divide by value.

You must select tx_clkout clock source as user clock 1 or 2. The calculated output frequency is shown in the frequency of the tx_clkout parameter.

The following example shows you how to configure the TX FGT PLL in core PLL mode for 200 MHz output frequency with 100 MHz reference clock frequency.
  1. Select the TX simplex PMA mode and specify the data rate as 1250Mbps.
  2. Select TX FGT PLL reference clock frequency as 100MHz.
  3. Enable TX user clock 1 and specify TX user clock divide by value to 50.
  4. Select tx_clkout clock source as user clock 1 and you can see the calculated 200MHz output frequency in the tx_clkout parameter.
The output frequency of the TX FGT PLL is the VCO frequency divided by TX user clock divide by value. In the example, if TX user clock divide by value is set to 25, the output frequency is 400MHz. You can modify the PMA data rate and the TX user clock divide by value to get the required output frequency for a given reference clock frequency.

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