F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.8.4. Reset Signals—Descriptions

Table 74.  Reset Signal Descriptions
Name Width Domain Direction Type Description
tx_reset 1 Asynchronous Input N/A TX reset input for TX PMAs and TX datapath. Must be kept asserted until tx_reset_ack is asserted. Applies to all TX channels in a F-Tile PMA/FEC Direct PHY Intel® FPGA IP instance.
tx_reset_ack 1 Asynchronous Output N/A TX fully in reset indicator.
rx_reset 1 Asynchronous Input N/A RX reset input for RX PMAs and RX datapath. Must be kept asserted until rx_reset_ack is asserted. Applies to all RX channels in a F-Tile PMA/FEC Direct PHY Intel® FPGA IP instance.
rx_reset_ack 1 Asynchronous Output N/A RX fully in reset indicator.
reconfig_pdp_reset 1 Asynchronous Input Datapath Avalon® Memory Mapped Interface Reconfiguration Interface Reset
reconfig_xcvr_reset 1 Asynchronous Input PMA Avalon® Memory Mapped Interface Active-high synchronous reset. Assert this signal to reset the PMA reconfiguration interface.
tx_ready 1 Asynchronous Output N/A Status port to indicate when TX PMAs and TX datapath are reset successfully and ready for data transfer.
rx_ready 1 Asynchronous Output N/A Status port to indicate when RX PMAs and RX datapath are reset successfully and ready for data transfer.
tx_am_gen_start 1 Asynchronous Output N/A When using FEC, indicates when to start sending alignment markers. This clears after tx_am_gen_2x_ack is asserted.
tx_am_gen_2x_ack 1 Asynchronous Input N/A When using FEC, you must indicate to the reset sequencer at least 2 alignment markers were sent since tx_am_gen_start is asserted. This signal should be deasserted after tx_am_gen_start is deasserted.

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