F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies

Table 90.  Preset Reference Clock and Output Frequencies
Mode of System PLL - System PLL Reference Clock (MHz) Output Frequency (MHz)
ETHERNET_FREQ_805_156 156.25 805.6640625
ETHERNET_FREQ_805_312 312.5 805.6640625
ETHERNET_FREQ_805_322 38. 322.265625 805.6640625
ETHERNET_FREQ_830_156 156.25 830.078125
ETHERNET_FREQ_830_312 312.5 830.078125
     
PCIE_FREQ_1000 100 1000
PCIE_FREQ_950 100 950
PCIE_FREQ_900 100 900
PCIE_FREQ_850 100 850
PCIE_FREQ_800 100 800
PCIE_FREQ_750 100 750
PCIE_FREQ_700 100 700
PCIE_FREQ_650 100 650
PCIE_FREQ_600 100 600
PCIE_FREQ_550 100 550
PCIE_FREQ_500 100 500
Table 91.  Port Connection Guidelines between F-Tile Reference and System PLL Clocks Intel® FPGA IP and F-Tile PMA/FEC Direct PHY Intel® FPGA IP
F-Tile Reference and System PLL Clocks Intel® FPGA IP F-Tile PMA/FEC Direct PHY Intel® FPGA IP
System PLL
out_systempll_clk system_pll_clk_link
FGT
out_refclk_fgt tx_pll_refclk_link, rx_cdr_refclk_link
in_cdrclk rx_cdr_divclk_link
FHT
out_fht_cmmpll_clk tx_pll_refclk_link, rx_cdr_refclk_link
38 This mode is not currently supported

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