F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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6.6. Connecting the F-tile PMA/FEC Direct PHY Design IP

After generating the RTL and supporting files for the F-Tile PMA/FEC Direct PHY Intel® FPGA IP and F-Tile Reference and System PLL Clocks Intel® FPGA IP, you connect the two IP together in the top level file (top.v) based on the connections in Figure 1. Verify the top-level connection before running the Design Analysis Compiler stage.

Table 102.   F-tile PMA/FEC Direct PHY Design IP Port Connections
F-Tile Reference and System PLL Clocks Intel® FPGA IP Ports F-Tile PMA/FEC Direct PHY Intel® FPGA IP Ports
out_refclk_fgt_0
  • tx_pll_refclk_link 40
  • rx_cdr_refclk_link
out_systempll_clk_0

System_pll_clk_link

40 Ports ending in "_link" must connect to the F-Tile Reference and System PLL Clocks Intel® FPGA IP. These ports cannot be simulated

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