6.6. Connecting the F-tile PMA/FEC Direct PHY Design IP
After generating the RTL and supporting files for the F-Tile PMA/FEC Direct PHY Intel® FPGA IP and F-Tile Reference and System PLL Clocks Intel® FPGA IP, you connect the two IP together in the top level file (top.v) based on the connections in Figure 1. Verify the top-level connection before running the Design Analysis Compiler stage.
|F-Tile Reference and System PLL Clocks Intel® FPGA IP Ports||F-Tile PMA/FEC Direct PHY Intel® FPGA IP Ports|