F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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Document Table of Contents

3.3.3.1. RX FGT PMA Interface Options

Figure 63. RX FGT PMA Interface Options in Parameter Editor
Table 33.   RX FGT PMA Interface Parameters
Parameter Values Description
RX FGT PMA Parameters
RX PMA interface FIFO mode

Register

Elastic

Selects the RX PMA Interface FIFO mode. Default value is Elastic.
Enable rx_pmaif_fifo_empty port On/Off Enables the port that indicates the RX PMA Interface FIFO's empty condition. Default value is Off.
Enable rx_pmaif_fifo_pempty port On/Off Enables the port that indicates the RX PMA Interface FIFO's partially empty condition. Default value is Off.
Enable rx_pmaif_fifo_pfull port On/Off Enables the port that indicates the RX PMA Interface FIFO's partially full condition. Default value is Off.
RX Core Interface Parameters
RX core interface FIFO mode

Phase compensation

Elastic

Specifies the mode for the RX Core Interface FIFO. Default value is Phase compensation.
Enable RX double width transfer On/Off Enables double width RX data transfer mode. In this mode, core logic can be clocked with a half rate clock. Default value is On.
RX core interface FIFO partially full threshold 10 Specifies the partially full threshold for the RX Core Interface FIFO. Default value is 10.
RX core interface FIFO partially empty threshold 2 Specifies the partially empty threshold for the RX Core Interface FIFO. Default value is 2.
Enable rx_fifo_full port On/Off Enables the optional rx_fifo_full status output port. This signal indicates when the RX core FIFO has reached the full threshold. This signal is synchronous with rx_clkout. Default value is Off.
Enable rx_fifo_empty port On/Off Enables the optional rx_fifo_empty status output port. This signal indicates when the RX core FIFO has reached the empty threshold. This signal is synchronous with rx_clkout. Default value is Off.
Enable rx_fifo_pfull port On/Off Enables the optional rx_fifo_pfull status output port. This signal indicates when the RX core FIFO has reached the specified partially full threshold. Default value is Off.
Enable rx_fifo_pempty port On/Off Enables the optional rx_fifo_pempty status output port. This signal indicates when the RX core FIFO has reached the specified partially empty threshold. Default value is Off.
Enable rx_fifo_rd_en port On/Off Enables the optional rx_fifo_rd_en control input port. This port is used for Elastic FIFO mode. Asserting this signal enables the read from RX core FIFO. You must enable this read enable when using Elastic FIFO. Default value is Off.
RX Clock Options
Selected rx_clkout clock source

Word Clock

Bond Clock

User Clock 1

User Clock 2

Sys PLL Clock

Sys PLL Clock Div2

Specifies the rx_clkout output port source. Default value is Sys PLL Clock Div2.
Frequency of rx_clkout Output Displays the frequency of rx_clkout in MHz based on rx_clkout source selection.
Enable rx_clkout2 port On/Off Enables the optional rx_clkout2 output clock. Default value is Off.
Selected rx_clkout2 clock source

Word Clock

Bond Clock

User Clock 1

User Clock 2

Sys PLL Clock

Sys PLL Clock Div2

Specifies the rx_clkout output port source. Default value is Word Clock.
rx_clkout2 clock div by 1, 2 Selects the rx_clkout2 divider setting that divides out the rx_clkout2 output port source. Default value is 1.
Frequency of rx_clkout2 Output Displays the frequency of rx_clkout2 in MHz based on rx_clkout2 source selection and rx_clkout2 clock divide by factor.
Selected rx_coreclkin clock network

Dedicated Clock

Global Clock

Specifies the type of clock network to use to route the clock signal to rx_coreclkin port. Dedicated Clock allows a higher maximum frequency (fmax) between the FPGA fabric and the FPGA fabric and RX Core interface FIFO. The number of Dedicated Clock lines are limited. Default value is Dedicated Clock.

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