F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing

This section details the steps you should follow to configure the F-Tile PMA/FEC Direct PHY Intel® FPGA IP in order to bring-up the FHT or FGT PMA for hardware testing using System Console in the Intel® Quartus® Prime software. You can configure the PMA analog settings to enable functions such as serial loopback, PRBS generators and checkers, to modify TX equalizer settings, and BER measurements.

You can choose either of the following methods to access the PMA registers via JTAG using System Console:

Note: You can also use the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP to access the PMA registers for hardware testing as described in Hardware Flow Using the F-Tile Global Avalon Memory-Mapped Interface Intel FPGA IP.

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