F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.1.1. PMA Direct Supported Modes

The F-Tile PMA/FEC Direct PHY Intel® FPGA IP supports the following for PMA Direct mode:

  • Supports FGT with NRZ and PAM4 modulation. 18
  • Supports FHT with NRZ and PAM4 modulation
  • Supports PMA clocking mode and System PLL clocking mode
  • Supports Duplex, TX simplex, and RX simplex modes
  • Supports TX simplex and RX simplex for both PMA Clocking and System PLL Clocking modes. Supports 8, 10, 16, 20, 32 and 64-bit PMA data widths for simplex mode.
  • Supports bonding mode for NRZ and PAM4 modulation modes
  • Supports configurable FIFO modes: PMA interface FIFO, F-tile interface FIFO, Core interface FIFO-elastic, phase compensation, and register modes
  • Supports configuring multiple hard IP block PMA and FEC instances within one IP instance
  • Supports TX and RX de-skew if the number of streams per PMA exceeds one
  • Supports up to 12 Preset modes.
Figure 54. PMA Direct Mode with PMA Clocking
Figure 55. PMA Direct Mode with System PLL Clocking
Table 24.  PMA Direct Mode Support

PMA

Modulation

PMA

Mode

Clocking

Mode

Double

Width/

Single

Width

PMA

Interface

Width

PMA

Interface

FIFO

(TX/RX)

F-tile

Interface

FIFO

(TX/RX19)

Core

Interface

FIFO

(TX/RX)

PAM4 FGT System Clocking DW 64, 32

Elastic/

Elastic

Phase Compensation/

Register

Phase Compensation/

Phase Compensation

SW 32

Elastic/

Elastic

Phase Compensation/

Register

Phase Compensation/

Phase Compensation

PMA

Clocking

DW 32

Phase Compensation/

Register

TX:

Register/

Phase Compensation

RX:

Register

TX:

Phase Compensation/

Elastic|

RX:

Phase Compensation/

Elastic

DW 64

Elastic/

Elastic

Phase Compensation/

Register

Phase Compensation/

Phase Compensation

FHT System Clocking DW 32, 64, 128

Elastic/

Elastic

Phase Compensation/

Register

Phase Compensation/

Phase Compensation

PMA

Clocking

DW 64, 128

Elastic/

Elastic

Phase Compensation/

Register

Phase Compensation/

Phase Compensation

NRZ FGT System Clocking SW 8,10, 16, 20, 32

Elastic/

Elastic

Phase Compensation/

Register

Phase Compensation/Phase Compensation
DW 8,10, 16, 20, 32

Elastic/

Elastic

Phase Compensation/

Register

Phase Compensation/

Phase Compensation

PMA

Clocking

SW 10, 16

Phase Compensation/

Register

Register/

Register

Phase Compensation/

Phase Compensation

10,20, 32

Phase Compensation/

Register

Register/

Register

Elastic/

Elastic

20, 32

Phase Compensation/

Register

TX:

Register/

Phase Compensation|

RX:

Register

Phase Compensation/

Phase Compensation

DW 20, 32

Phase Compensation/

Register

TX:

Register/

Phase Compensation|

RX:

Register

Phase Compensation/

Phase Compensation

20, 32

Phase Compensation/

Register

Register/

Register

Elastic/

Elastic

FHT System Clocking DW 32, 64

Elastic/

Elastic

Phase Compensation/

Register

Phase Compensation/

Phase Compensation

SW 32

Elastic/

Elastic

Phase Compensation/

Register

Phase Compensation/

Phase Compensation

PMA

Clocking

SW / DW 32

Phase Compensation/

Register

TX:

Register/

Phase Compensation|

RX:

Register

Phase Compensation/

Phase Compensation

DW 64

Elastic/

Elastic

Phase Compensation/

Register

Phase Compensation/

Phase Compensation

18 Refer to PMA Data Rate Ranges by Datapath Clocking Mode for the supported data rate.
19 In PMA direct mode, RX F-tile interface FIFO is always set to Register mode. You cannot configure this in the PMA/FEC Direct PHY Intel FPGA IP.

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