F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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Document Table of Contents

6.1. Implementing the F-tile PMA/FEC Direct PHY Design

Note: This topic through Connecting the F-tile PMA/FEC Direct PHY Design IP explains how to implement a PMA/FEC Direct design by instantiating and connecting the necessary IP components. You can alternatively use the Example Design options that Example Design Generation describes to implement an example design.

This design implementation requires the following IP available from the Intel® Quartus® Prime Pro Edition software IP Catalog:

  • F-Tile PMA/FEC Direct PHY Intel® FPGA IP
  • F-Tile Reference and System PLL Clocks Intel® FPGA IP

The F-Tile PMA/FEC Direct PHY Intel® FPGA IP is the primary IP component for PMA and FEC direct implementation. This IP provides direct access to the F-tile PMA block features for both FGT and FHT.

To customize and instantiate the IP for your protocol implementation, you specify parameter values for the F-Tile PMA/FEC Direct PHY Intel® FPGA IP and generate the IP RTL and supporting files from the Intel® Quartus® Prime parameter editor.

The top-level file generated with the IP instance includes all the available ports for your configuration. You use these ports to connect the F-Tile PMA/FEC Direct PHY Intel® FPGA IP to other IP components in your design. These include connections to the respective reference clock pins and system PLL clock outputs from the F-Tile Reference and System PLL Clocks Intel® FPGA IP, TX and RX parallel data ports, as well as TX and RX serial data pins.

Figure 92 shows the connections between the IP design blocks required for the F-tile PMA/FEC Direct PHY design. The diagram illustrates the connections between the F-Tile Reference and System PLL Clocks Intel® FPGA IP, the Soft Reset Controller (that instantiates automatically after running Design Analysis), and the user-provided MAC/PCS IP core into the parallel data bus to the F-Tile PMA/FEC Direct PHY Intel® FPGA IP.

Figure 92.  F-tile PMA/FEC Direct PHY Design IP Connections
Note: (*)For full port lists, including the reconfig_pdp_avmm and reconfig_xcvr_avmm signals, refer to PMA Avalon Memory Mapped Interface Signals and Datapath Avalon Memory Mapped Interface Signals.

The following topics describe PHY IP parameterization, connection, simulation, and tile placement planning for the design:

  1. Instantiating the F-Tile PMA/FEC Direct PHY Intel FPGA IP
  2. Instantiating the F-Tile Reference and System PLL Clocks Intel FPGA IP
  3. Enabling Custom Cadence Generation Ports and Logic
  4. Connecting the F-tile PMA/FEC Direct PHY Design IP
  5. Simulating the F-Tile PMA/FEC Direct PHY Design
  6. F-tile Interface Planning

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