F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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2.2.7. Clock Rules and Restrictions

  • A stable and running reference clock is not required to configure the FPGA at power-up.
  • A reference clock must be up and stable before releasing the connected hard IP resets.
  • After releasing the reset, the system PLL reference clock must be stable; it must be present throughout the operation and must not go down. If you are not able to adhere to this, you must reconfigure the device.
  • After releasing the reset, the reference clock that drives the FHT microcontroller must be stable; it must be present throughout the operation, must not change the frequency, and must not go down. If you are not able to adhere to this, you must reconfigure the device.
  • The baud rate or line frequency of two adjacent FHT lanes must be either exactly the same (driven by the same reference clock and receiving signals from a family of transmitters synchronized to the same reference clock) or separated at least by 2,000 ppm. This is to eliminate lane-to-lane interaction.
  • Each hard IP instance, for example, 25GbE with FEC, CPRI 24G with FEC, and 50GbE FEC Direct, placed in the same FEC core must use the same system PLL.
  • Each Ethernet hard IP instance running IEEE 1588 precision time protocol must use the same system PLL.
  • All lanes that are part of the same interface, for example, the eight lanes of a 400GbE, must use the same system PLL.
  • TX simplex and RX simplex must use the same system PLL unless they are both using PMA Direct's PMA clocking mode.
  • The system PLL must not be dynamically reconfigured. In addition, the system PLL input and output clock frequencies must not be dynamically reconfigured. If this is not followed, you must reconfigure the device.
  • All hard IPs that are assigned to a dynamic reconfiguration group must use the same system PLL.
  • System PLL clocking mode must be used for data rates between 29 Gbps and 32 Gbps NRZ.

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