F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.11. Configuration Registers

You can access the F-Tile PMA registers using the PMA Avalon® memory-mapped interface on each lane. You can access the F-Tile PMA/FEC Direct PHY Intel® FPGA IP soft CSRs using the datapath Avalon® memory-mapped interface.

Write operations to a read-only register field have no effect. Read operations that address a reserved register return an unspecified result. Write operations to reserved registers have an undefined effect. Accesses to registers that do not exist in your IP core variation, or to register bits that your IP core variation does not define, have an unspecified result. Consider these registers and register bits reserved. Although you can only access registers in 32-bit read and write operations, do not attempt to write or ascribe meaning to values in undefined register bits.

The F-tile PMA Register Map contains the reconfiguration register information for:
  • PMA and FEC Direct PHY soft CSR registers
  • FHT PMA registers
  • FGT PMA registers
The following section describes the register map for each area and how to access the registers.

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